1. Field of Invention
The present invention relates to a microprocessor, and more particularly to a microprocessor with reduced pin counts.
2. Related Art
Recently, the technology is progressing rapidly. The technology of the single-chip microprocessor is applied to many consumer electronic products, such as televisions, displays or even motors.
FIG. 1 shows pins of a conventional 8032 single-chip microprocessor. Referring to FIG. 1, several important pins will be introduced. The pins P0.0 to P0.7, P1.0 to P1.7, P2.0 to P2.7 and P3.0 to P3.7 are respectively the pins of four ports, including port(0), port(1), port(2) and port(3). The symbols beginning with P0 correspond to the port(0), the symbols beginning with P1 correspond to the port(1), the symbols beginning with P2 correspond to the port(2), and the symbols beginning with P3 correspond to the port(3). The pin ALE outputs a lower bit address latch control signal for controlling an external latch to latch a lower bit address bus outputted from the port P0. The pin PSEN outputs a program access enable control signal to enable an external memory so that a data access operation on the external memory can be performed.
FIG. 2 is a circuit block diagram showing the conventional 8032 single-chip microprocessor. Referring to FIG. 2, the circuit includes an 8032 single-chip microprocessor 201, a latch circuit 202 and a flash memory 203.
FIG. 3 shows waveforms used in the circuit of FIG. 2. Generally speaking, as shown in FIGS. 2 and 3, the port P0 (P0[7] to P0[0]) is used for outputting lower bit addresses A0 to A7 to the external memory (the flash memory 23), and performing the data access operation on the flash memory 203. The port P2 (P2[7] to P2[0]) is used for outputting higher bit addresses A8 to A15.
During the data access operation on the flash memory 203, four clocks T1 to T4 constitute a cycle. As the clock T1 rises, the voltage of the access enable pin PSEN is changed from the logic low voltage to the logic high voltage. At this time, the data bus of the flash memory 203 is in the high impedance state. Next, the voltage of the address latch pin ALE is also changed from the logic low voltage to the logic high voltage, while the microprocessor 201 starts to output the lower bit addresses A0 to A7 from the port P0. Then, the microprocessor 201 starts to output the higher bit addresses A8 to A15 from the port P2 at the rising edge of the clock T2. Then, when the voltage of the address latch pin ALE is changed from the logic high voltage to the logic low voltage, the lower bit addresses A0 to A7 are latched by the latch circuit 202. Finally, the port P0 is set to the high impedance state at the rising edge of the clock T2. When the voltage of the access enable pin PSEN is changed from the logic high voltage to the logic low voltage, the flash memory 203 outputs or writes data according to the /WR control signal.
According to the above-mentioned operations, it is obtained that the microprocessor 201 needs at least 19 pins to maintain the above-mentioned operation. When the product is being researched and developed, the software often needs to be updated. Thus, it is more flexible to adopt the external flash memory 203. During the implement of the product, the software needs not to be updated. Thus, the software is directly written into the microprocessor 201. For example, the original 8032 microprocessor is replaced with the 8051 microprocessor. However, the above-mentioned microprocessor 201 still has extra 19 pins left after the product has been developed. So, the following defects will be caused.
First, the area of the integrated circuit of the microprocessor cannot be reduced. In the integrated circuit, the number of bonding pads has to be greater than or equal to the pin counts, so the die size of the integrated circuit cannot be effectively reduced.
Second, the layout of the product is restricted. After the product has been developed, the opportunity of using these pins (P0.1 to P0.8; P2.1 to P2.8) is relatively decreased. However, these pins still have to occupy a relative large area to cause the restriction in the layout of the printed circuit board.